Title :
PreTrans: Reducing TLB CAM-search via page number prediction and speculative pre-translation
Author :
Jiachen Xue ; Thottethodi, Mithuna
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
The need for fast address translation within tight time constraints (before L1 tag check but after effective address computation) imposes many design constraints. The freedom from such constraints can potentially lead to lower TLB energy costs. In this paper, we observe that (1) data accesses commonly use base-displacement addressing modes in which the effective address is computed as the sum of a base and a displacement, and (2) the effective page numbers are predictable once the base address is known. Further, it is easy to cache address translations alongside the predicted page numbers thus enabling speculative address translation that can filter accesses to the TLB. The two observations enable our PreTrans design in which (a) a speculative translation is available based solely on the base address, and (b) the translation is available simultaneously with the effective (virtual) address. PreTrans replaces most of the energy-expensive CAM-lookups for TLB access with RAM lookups, which translates to significant power improvements in the TLB.
Keywords :
cache storage; information retrieval; random-access storage; table lookup; CAM-lookups; L1 tag check; PreTrans; RAM lookups; TLB CAM-search; TLB energy costs; base-displacement addressing modes; cache address translations; data access; page number prediction; speculative address translation; speculative pre-translation; time constraints; virtual address; Accuracy; Benchmark testing; Computer architecture; Delays; Organizations; Program processors; Registers; Power; Prediction; Speculation; TLB;
Conference_Titel :
Low Power Electronics and Design (ISLPED), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4799-1234-6
DOI :
10.1109/ISLPED.2013.6629320