"Linearization Techniques at the Device and Circuit Level" (Invited)

Author

de Vreede, Leo C. N. ; van der Heijden, Mark P.

Author_Institution

Dept. of Microelectron., Delft Univ. of Technol.

fYear

2006

fDate

8-10 Oct. 2006

Firstpage

1

Lastpage

8

Abstract

Modern telecommunication applications set high demands on transceiver technology and design in terms of speed, noise, linearity and power consumption. This paper provides an overview of techniques, at the device and circuit level, which improve the classical DC power consumption / linearity trade-off found in (bipolar) telecommunication circuits

Keywords

linearisation techniques; transceivers; CMOS linearization; DC power consumption; current-mode; device optimization; harmonic load-pull; linearity trade-off; linearization techniques; nonlinear distortion; out-of-band termination; power amplifier; telecommunication circuits; transconductance; Distortion; Energy consumption; FETs; Integrated circuit technology; Laboratories; Linearity; Linearization techniques; Transceivers; Transconductance; Voltage; CMOS linearization; IM3 cancellation; Nonlinear distortion; bipolar; current-mode; device optimization; feedback; harmonic load-pull; out-of-band termination; power amplifier; transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 2006

Conference_Location

Maastricht

ISSN

1088-9299

Print_ISBN

1-4244-0458-4

Electronic_ISBN

1088-9299

Type

conf

DOI

10.1109/BIPOL.2006.311128

Filename

4100196