Title :
Low power 2.5 Gb/s serializer for SOC applications
Author :
Iniewski, K. ; Syrzycki, M.
Author_Institution :
Simon Fraser Univ., Burnaby, BC, Canada
Abstract :
2.5 Gb/s serializer suitable for system-on-the-chip (SOC) implementation is presented. Phase lock loop architecture is of type IV that results in superior performance for power supply rejection ratio (PSRR). The circuit has been implemented in 0.18μm standard CMOS process, occupies 1230 μm by 248μm and dissipates 128mW. The serializer has been designed for OC-48 SONET/SDH but can be used in variety of other communication and computer protocols and applications like Infiniband, RAPID I/O (RIO) and PCI Express.
Keywords :
CMOS digital integrated circuits; SONET; low-power electronics; phase locked loops; protocols; synchronous digital hierarchy; system-on-chip; 0.18 microns; 128 mW; 2.5 Gbit/s; Infiniband; OC-48 SONET; PCI Express; RAPID I-O; RIO; SDH application; SOC applications; communication protocol; computer protocols; low power serializer; phase lock loop architecture; power supply rejection ratio; standard CMOS process; system-on-the-chip implementation; Circuit synthesis; Clocks; Driver circuits; Phase locked loops; Power dissipation; Power supplies; Protocols; SONET; Signal synthesis; Synchronous digital hierarchy;
Conference_Titel :
VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on
Print_ISBN :
0-7695-2097-9
DOI :
10.1109/ISVLSI.2004.1339532
