DocumentCode
3498431
Title
Litho-aware and low power design of a secure current-based physically unclonable function
Author
Kumar, Ravindra ; Burleson, Wayne
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Massachusetts Amherst, Amherst, MA, USA
fYear
2013
fDate
4-6 Sept. 2013
Firstpage
402
Lastpage
407
Abstract
Physically Unclonable Functions (PUFs) are lightweight cryptographic primitives for generating unique signatures from complex manufacturing variations. In this work, we present a current-based PUF designed using a generalized lithographic simulation framework for improving inter-die and inter-wafer uniqueness. The sensitivity of the circuit to manufacturing variations is enhanced by placing the gate structures at pitches closer to forbidden zone, where the sensitivity of Critical Dimension (CD) to the pitch variations is very high. Simulation results show that the litho-aware current based PUF has improved inter- and intra-distance over the conventional current-based PUF. The litho-aware PUF consumes about 0.034 pico joules of energy per response bit, which is substantially better than delay-based PUF implementations.
Keywords
cryptography; integrated circuit design; lithography; low-power electronics; complex manufacturing variations; critical dimension; forbidden zone; gate structures; generalized lithographic simulation framework; inter-die uniqueness; inter-wafer uniqueness; lightweight cryptographic primitives; litho-aware current based PUF; low power design; physically unclonable function; pitch variations; Integrated circuit modeling; Integrated circuit reliability; Logic gates; Semiconductor device modeling; Sensitivity; Transistors; Physically unclonable functions; forbidden pitches; hardware security; sub-wavelength lithography;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics and Design (ISLPED), 2013 IEEE International Symposium on
Conference_Location
Beijing
Print_ISBN
978-1-4799-1234-6
Type
conf
DOI
10.1109/ISLPED.2013.6629331
Filename
6629331
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