Deep Trench NPN Transistor for Low-RON ESD Protection of High-Voltage I/Os in Advanced Smart Power Technology

Author

Gendron, A. ; Salamero, C. ; Nolhier, N. ; Bafleur, M. ; Renaud, P. ; Besse, P.

Author_Institution

Freescale Semicond., Toulouse Cedex

fYear

2006

fDate

8-10 Oct. 2006

Firstpage

1

Lastpage

4

Abstract

An innovative self-biased NPN transistor dedicated to the ESD protection of high voltage I/Os is presented. To fulfil a high clamping voltage / low on-state resistance specification, the authors have taken benefit of specific technology features, as deep insulation trenches, low-doped epitaxy and high-doped buried layer. First, the guidelines allowing the increase of the clamping voltage and the lowering of the on-state resistance are defined, based on an accurate description of the physical mechanisms involved during an ESD stress. Then, the proposed NPN transistor is described, and the results of measurements and TCAD simulations are presented. Excellent capabilities as 40 Volt clamping voltage, zero on-state resistance and I_t2 higher than 5 Ampere have been achieved

Keywords

bipolar integrated circuits; buried layers; electrostatic discharge; isolation technology; power bipolar transistors; power integrated circuits; technology CAD (electronics); 40 V; ESD protection; TCAD simulations; advanced smart power technology; deep insulation trenches; deep trench NPN transistor; high-doped buried layer; high-voltage I/O; low-doped epitaxy; self-biased NPN transistor; Clamps; Electrical resistance measurement; Electrostatic discharge; Epitaxial growth; Guidelines; Insulation; Low voltage; Protection; Stress; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 2006

Conference_Location

Maastricht

ISSN

1088-9299

Print_ISBN

1-4244-0458-4

Electronic_ISBN

1088-9299

Type

conf

DOI

10.1109/BIPOL.2006.311138

Filename

4100206