Deep Trench NPN Transistor for Low-RON ESD Protection of High-Voltage I/Os in Advanced Smart Power Technology

An innovative self-biased NPN transistor dedicated to the ESD protection of high voltage I/Os is presented. To fulfil a high clamping voltage / low on-state resistance specification, the authors have taken benefit of specific technology features, as deep insulation trenches, low-doped epitaxy and high-doped buried layer. First, the guidelines allowing the increase of the clamping voltage and the lowering of the on-state resistance are defined, based on an accurate description of the physical mechanisms involved during an ESD stress. Then, the proposed NPN transistor is described, and the results of measurements and TCAD simulations are presented. Excellent capabilities as 40 Volt clamping voltage, zero on-state resistance and I_t2 higher than 5 Ampere have been achieved