64-bit low threshold voltage high-speed conditional carry adder by complementary pass-transistor logic

Author

Cheng, Kuo-Hsing ; Cheng, Shun-Wen ; Liao, Che-Yu

Author_Institution

Nat. Central Univ., Chung-li, Taiwan

fYear

2004

fDate

19-20 Feb. 2004

Firstpage

233

Lastpage

236

Abstract

A 64-bit low threshold voltage conditional carry adder using complementary pass-transistor logic for low-voltage and high-speed application was presented. The improved conditional sum addition rule can reduce the number of internal nodes and multiplexers in the adder design. And reducing the threshold voltage increases the speed of operation. Thus, a low threshold voltage design is favourable for implementing low-voltage, high-speed arithmetic systems. The performances of such circuits are compared with that of normal and zero threshold voltage schemes; the proposed circuit gets the lowest power-delay product and energy-delay product from 1.0V to 2.5V. The circuit is demonstrated to balance between power consumption and performance effectively.

Keywords

CMOS logic circuits; adders; high-speed techniques; logic design; threshold logic; 62 bit; CPL; VLSI; adder design; complementary pass-transistor logic; conditional sum addition rule; energy-delay product; high-speed application; high-speed arithmetic systems; high-speed conditional carry adder; low threshold voltage adder; low threshold voltage design; low-voltage application; low-voltage arithmetic systems; normal threshold voltage schemes; power consumption; power-delay product; zero threshold voltage schemes; Adders; Arithmetic; Circuits; Digital signal processing; Energy consumption; Logic; Multiplexing; Power dissipation; Threshold voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on

Print_ISBN

0-7695-2097-9

Type

conf

DOI

10.1109/ISVLSI.2004.1339539

Filename

1339539