The use of rapid thermal processing to improve performance of sub-half micron CMOS with and without salicide

The dependence of performance and parasitic resistances on source/drain implant anneal conditions and on back-end-of-line maximum temperature is evaluated for (1) salicided CMOS using n⁺/p⁺ poly gates with surface channel PMOS and for (2) unsalicided CMOS using all n⁺ poly gates with buried channel PMOS. The gate oxide thickness used is 6 nm. Both the NMOS and PMOS effective channel lengths are near 0.25 mu m. The results show that CMOS circuit design can include wide transistors and asymmetrically placed contacts if salicide is used with RTP anneal of source/drain and back-end-of-line temperatures no higher than 725 C.