Towards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow models

As SystemC gains popularity as a modelling language of choice for system-on-chip (SOC) designs, heterogeneous modelling in SystemC and efficient simulation become increasingly important. However, in the current reference implementation, all SystemC models are simulated through a non-deterministic discrete-event simulation kernel, which schedules events at run-time. This sometimes results in too many delta cycles hindering the simulation performance of the model. The SystemC language also seems to target this simulation kernel as the target simulation engine making it difficult to express different models of computation (MOC) naturally in SystemC. In an SOC model, different components may need to be naturally expressible in different MOCs. Some of these components may be amenable to static scheduling based simulation or other pre-simulation optimization techniques. Our goal is to create a simulation framework for heterogeneous SystemC models, to gain efficiency and ease of use within the framework of SystemC reference implementation. In this work, we focus on synchronous data flow (SDF) models, where the rates of data produced and consumed by a data flow node/block are known a priori. Compile time knowledge of these rates allows the use of static scheduling resulting to significant improvement in simulation efficiency. We propose source level hints to be provided by the model designer to help express SDF more naturally and to make the new simulation kernel execute special functionalities. Our experiments show significant improvement in simulation time over the original models.