Title :
Incorporating power reduction mechanism in arithmetic core design
Author :
Hong, Sangjin ; Chin, Shu-Shin
Author_Institution :
Dept. of Electr. & Comput. Eng., Stony Brook Univ., NY, USA
Abstract :
A novel supply voltage switching mechanism for reducing power dissipation of array structures is presented. The mechanism eliminates power dissipated by the glitching while it maintains the speed. The mechanism can be applied to either fully combinational or pipelined array structures such as parallel multipliers and/or CORDICs. The mechanism is easily incorporated such that no circuit change in the existing array structure is necessary.
Keywords :
combinational switching; multiplying circuits; pipeline arithmetic; power supply circuits; CORDIC; arithmetic core design; combinational structures; glitching; parallel multipliers; pipelined array structures; power reduction mechanism; supply voltage switching mechanism; Adders; Arithmetic; Clocks; Delay; Logic arrays; Pipeline processing; Power dissipation; Registers; Switches; Voltage;
Conference_Titel :
VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on
Print_ISBN :
0-7695-2097-9
DOI :
10.1109/ISVLSI.2004.1339544
