Pipeline design based on self-resetting stage logic

In this paper, we present a novel synchronization approach to support data flow in clockless designs using single-rail encoding. This approach is based on self-resetting stage logic in which a pipeline stage resets itself before starting the next execution cycle. As such, a stage goes through a reset phase when its output is null, and an evaluate phase when its output is the result of the evaluation of its inputs. To insure a proper data flow, a latch-based synchronization mechanism is proposed, which yields an efficient and simple uni-directional handshaking scheme between stages that accommodates easy implementation. A concept design of a four-bit 16-stage pipeline is presented to illustrate the inner workings of self-resetting stage logic and its data-flow synchronization mechanism. The pipeline performance is examined through a detailed signal timing analysis. This analysis reveals some insights on how the duration of the evaluate phase gradually increases while the duration of the reset phase and the latch enable gradually decreases toward the left stages of the pipeline. This gradual decrease in the duration of the enable of the latches between stages is used to derive a bound on the maximum possible depth of the pipeline.