A configurable pipelined state machine as a hybrid ASIC and configurable architecture

We present a configurable FSM where all units relevant for control and transition logic are configurable while the basic structural components like state registers are built of fixed logic. Implemented as part of an ASIC, FSMs are efficient and fast, but inflexible. When realized using FPGA hardware, they are flexible but inefficient in terms of area and speed. We describe the architecture of a combined approach faster and smaller than an FPGA implementation while providing full programmability.