DocumentCode
3498756
Title
Detection and diagnosis of faulty quantum circuits
Author
Paler, Alexandru ; Polian, Ilia ; Hayes, John P.
Author_Institution
Fac. of Comput. Sci. & Math., Univ. of Passau, Passau, Germany
fYear
2012
fDate
Jan. 30 2012-Feb. 2 2012
Firstpage
181
Lastpage
186
Abstract
A new approach to detecting and diagnosing faults in quantum circuits is introduced. In order to account for the probabilistic nature of quantum circuits, collections of test experiments, called binary tomographic tests (BTTs), are generated. A BTT can identify a fault with respect to some user-defined confidence threshold τ. We present an algorithm to generate BTTs that either detect, or ensure the absence of, all modeled faults in a given circuit. We also present an adaptive diagnostic method to locate quantum faults. While classical circuits, even probabilistic ones, only handle ordinary probabilities, quantum circuits deal with quantum states, which have phase as an extra probabilistic parameter. The tomographic testing methods introduced previously for probabilistic circuits are unable to detect differences in phase, and therefore leave many quantum faults undetected. In contrast, we develop a design-for-test method which is specifically intended to detect faults that only affect the phase of a quantum state. We give experimental results for benchmark and random circuits which show high coverage of quantum faults by BTTs, and good resolution in the case of the adaptive diagnosis method.
Keywords
benchmark testing; design for testability; fault diagnosis; integrated circuit reliability; probability; quantum gates; adaptive diagnostic method; benchmark circuits; binary tomographic tests; confidence threshold; design for test method; faulty quantum circuit detection; faulty quantum circuit diagnosis; probabilistic circuits; quantum states; random circuits; Circuit faults; Integrated circuit modeling; Logic gates; Quantum computing; Testing; Tomography; Vectors; Probabilistic testing; design for test; fault diagnosis; quantum circuits; test generation;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific
Conference_Location
Sydney, NSW
ISSN
2153-6961
Print_ISBN
978-1-4673-0770-3
Type
conf
DOI
10.1109/ASPDAC.2012.6164942
Filename
6164942
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