Clock-constrained simultaneous allocation and binding for multiplexer optimization in high-level synthesis

This paper proposes a novel simultaneous allocation and binding method in high-level synthesis, which minimizes the circuit area including multiplexers (MUXs) under a clock constraint. Most existing works on binding minimize MUXs under given allocation by minimizing the number of inter connections, but do not care where the MUXs would be in serted in a circuit. As a result, they cannot guarantee the re quired clock frequency and often violate the clock constraint. On the contrary, our work globally optimizes binding and al location for FUs and registers while meeting the clock constraint by considering where MUXs would be inserted. Our work is formulated as an ILP problem. Also, an effective ILP-based heuristic for non-small designs is presented. Ex perimental results demonstrate that our work satisfies the clock constraint with the minimum circuit area.