Tier-adaptive-voltage-scaling (TAVS): A methodology for post-silicon tuning of 3D ICs

Author

Chae, Kwanyeob ; Mukhopadhyay, Saibal

Author_Institution

Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2012

fDate

Jan. 30 2012-Feb. 2 2012

Firstpage

277

Lastpage

282

Abstract

This paper presents tier-adaptive-voltage-scaling (TAVS) as a post-silicon tuning methodology for improving parametric yield of 3D integrated circuits considering die-to-die and within-die process variations. The TAVS methodology senses process corners of individual tiers using on-tier delay sensors and adapt the supply voltage of each tier. The overall TAVS architecture is presented and the circuit issues associated with design of 3D level shifters are discussed. Circuit level simulation and statistical analysis of the TAVS architecture in predictive 45nm technology show the possibility of 26%-39% reduction in chip delay distribution.

Keywords

circuit simulation; elemental semiconductors; integrated circuit design; integrated circuit modelling; integrated circuit yield; nanoelectronics; silicon; statistical analysis; three-dimensional integrated circuits; 3D IC; 3D integrated circuit; 3D level shifter; Si; TAVS architecture; TAVS methodology; chip delay distribution; circuit level simulation; die-to-die process; on-tier delay sensor; post-silicon tuning; size 45 nm; statistical analysis; tier-adaptive-voltage-scaling; within-die process; Delay; Regulators; Sensors; Three dimensional displays; Threshold voltage; Through-silicon vias; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific

Conference_Location

Sydney, NSW

ISSN

2153-6961

Print_ISBN

978-1-4673-0770-3

Type

conf

DOI

10.1109/ASPDAC.2012.6164958

Filename

6164958