A modular 0.8 mu m technology for high performance dielectric antifuse field programmable gate arrays

A high performance dielectric based antifuse field programmable gate array (FPGA) process has been developed using a standard 0.8 mu m double layer metal CMOS process. The process requires two additional self-contained modules to implement both the programmable interconnect element and the high voltage transistors required to program the antifuses. The antifuse is 8.4 nm ONO dielectrics. The high voltage transistors are 35 nm gate oxide with a novel S/D implant offset to field oxide edge and gate edge to achieve 20 volts programming voltage without disturbing the standard CMOS transistors. A family of FPGA´s was developed using this technology yielding system-level performance of 75 MHz and 16 bit counter performance in excess of 125 MHz.