Quantitative Analysis of Errors in On-Wafer S-Parameter De-embedding Techniques for High Frequency Device Modeling

The de-embedding of intrinsic device parameters from on-wafer measurements is a central problem in high frequency device measurement and modeling. The first quantitative analysis of the errors associated with de-embedding on-wafer s-parameter measurements of 90nm bulk FETs and 130nm SiGe HBTs taking into account the effects of non-ideal standards is presented. Four different on-wafer de-embedding techniques are examined. Electromagnetic (EM) simulations accounting for these non-idealities are used to compare different methods. It is demonstrated that unwanted parasitics in standards can significantly affect parameters extracted using more complex de-embedding techniques. The most sensitive standard is identified and an optimized design is presented