DocumentCode
3499619
Title
GaAs digital arithmetic subsystem for high data-rate signal processing
Author
Irvine, J.A. ; Gorder, G.E. ; Singh, H.P. ; Sadler, R.A.
Author_Institution
ITT Defense Commun. Div., Nutley, NJ, USA
fYear
1988
fDate
23-26 Oct. 1988
Firstpage
215
Abstract
A high-speed, low-power GaAs digital arithmetic subsystem has been developed which performs 8-bit arithmetic and logic functions required for signal processing. The subsystem integrates seven GaAs integrated circuits, including an 8*8-bit multiplier/accumulator, two 4-bit arithmetic logic units, three logical multiplexers, and a logical demultiplexer, using a commercially available prototype board. The subsystem operates at a clock rate as high as 325 MHz, the maximum clock rate of the multiplier, with a delay of 9.6 ns. The power dissipation of the subsystem is 1.4 W, excluding output driver power, at a power supply voltage of 1.4 V.<>
Keywords
III-V semiconductors; digital arithmetic; gallium arsenide; logic circuits; multiplexing equipment; signal processing equipment; 1.4 V; 1.4 W; 325 MHz; 4 bit; 8 bit; 9.6 ns; GaAs; III-V semiconductors; delay; digital arithmetic subsystem; high data-rate signal processing; logic functions; logic units; logical demultiplexer; logical multiplexers; power dissipation; Clocks; Delay; Digital arithmetic; Digital signal processing; Gallium arsenide; Logic circuits; Logic functions; Multiplexing; Power dissipation; Prototypes;
fLanguage
English
Publisher
ieee
Conference_Titel
Military Communications Conference, 1988. MILCOM 88, Conference record. 21st Century Military Communications - What's Possible? 1988 IEEE
Conference_Location
San Diego, CA, USA
Type
conf
DOI
10.1109/MILCOM.1988.13396
Filename
13396
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