DocumentCode
3499692
Title
A 12-bit EEPROM trimmed analog-to-digital converter
Author
Mayes, MichaeI K. ; Chin, Sing
Author_Institution
National Semiconductor, Santa Clara, CA, USA
fYear
1993
fDate
1993
Firstpage
331
Lastpage
335
Abstract
A 12-bit 2.5 M sample/second low power analog-to-digital converter (ADC) was designed. Linearity errors less than 1/2 LSB have been achieved using an EEPROM memory driving a correction DAC. A pipelined-multistep architecture results in conversion times of 400 ns while drawing less than 20 mA on a single 5 volt supply. The ADC conversion consists of 3-flash-steps, each sharing 16 sampled-data comparators, and driven by code-dependent correction factors to compensate for resistor mismatch.
Keywords
EPROM; analogue-digital conversion; pipeline processing; 100 ns; 12 bit; 20 mA; 5 V; ADC conversion; EEPROM memory; EEPROM trimmed analog-to-digital converter; code-dependent correction factors; correction DAC; linearity error; pipelined-multistep architecture; sampled-data comparators; Analog-digital conversion; CMOS process; Capacitors; Circuits; EPROM; Error correction; Linearity; Resistors; Sampling methods; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on
Conference_Location
Taipei, Taiwan
ISSN
1524-766X
Print_ISBN
0-7803-0978-2
Type
conf
DOI
10.1109/VTSA.1993.263674
Filename
263674
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