DocumentCode :
3499739
Title :
Relaxed synchronization technique for speeding-up the parallel simulation of multiprocessor systems
Author :
Yun, Dukyoung ; Kim, Sungchan ; Ha, Soonhoi
Author_Institution :
Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., Seoul, South Korea
fYear :
2012
fDate :
Jan. 30 2012-Feb. 2 2012
Firstpage :
449
Lastpage :
454
Abstract :
For design verification of an MPSoC, a virtual prototyping system has been widely used as a cheap and fast method without a hardware prototype. It usually consists of component simulators working together in a single simulation host. As the number of component simulators increases, the simulation performance degrades significantly due to occurrence of frequent inter-simulator communication. In this paper, to boost up the simulation speed further, we propose a novel technique, called relaxed synchronization, which uses a simulation cache at each component simulator for simulation purpose. Like an architectural cache that reduces the main memory access frequency, a simulation cache reduces the count of synchronous communication effectively between the corresponding component simulator and the simulation backplane. When a read or write request to a shared memory is made, a cache line, not a single element, is transferred to utilize the space and temporal locality for simulation. The proposed technique is based on an assumption that the application program uses a relaxed memory model. Through experiments with real-life applications, it is proved that the proposed approach improves the simulation performance by up to 330 %.
Keywords :
cache storage; circuit simulation; integrated circuit design; parallel architectures; performance evaluation; shared memory systems; synchronisation; system-on-chip; virtual prototyping; MPSoC design Sungchan verification; application program; component simulators; intersimulator communication; multiprocessor system; multiprocessor system-on-chip; relaxed memory model; relaxed synchronization technique; shared memory; simulation cache; space locality; synchronous communication; temporal locality; virtual prototyping system; Asynchronous communication; Backplanes; Computational modeling; Kernel; Program processors; Semiconductor process modeling; Synchronization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific
Conference_Location :
Sydney, NSW
ISSN :
2153-6961
Print_ISBN :
978-1-4673-0770-3
Type :
conf
DOI :
10.1109/ASPDAC.2012.6164990
Filename :
6164990
Link To Document :
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