Design of a system-on-a-chip for pattern recognition

Addresses the design and specification of a heterogeneous HW/SW architecture of a SOC (system-on-a-chip) for pattern recognition. In this design, a RISC processor is used along with specialized optimized coprocessors all articulated around a system bus (PI-bus). Once the algorithms involved are presented, we investigate the hardware/software codesign methodology, relying on the use of a system level simulator and extensive reutilization of arithmetic and signal processing operator library. We then present the system architecture and finally the VLSI physical integration. We conclude by giving results on the performance of the system and its VLSI characteristics