Due window scheduling for IC sort and test with precedence constraints via Lagrangian relaxation

In an integrated circuit (IC) manufacturing environment, a combination of tester, prober, and some hardware facilities (e.g. loadboard and prober card) is needed for water sort while a combination of tester, handler, and some hardware facilities (e.g. loadboard and interface board) is needed for final test. To schedule both sorting and testing at the same time, the resource constraints on testers, probers, handlers and hardware have to be dealt with. Also, a product on a test floor may need to be processed through a number of stages in a specific order. Often each product is given a due window, an interval in time rather than a point in time. Any product completed after its latest due date is considered tardy and before its earliest due date will incur a holding cost. An IC test floor scenario is modeled as an integer programming formulation. The objective is to minimize both earliness and tardiness subject to resource constraints, precedence constraints, and processing time requirements. It is then solved by the Lagrangian relaxation approach, which relaxes the resource constrains and precedence constraints. An important advantage of this approach is that it provides a lower bound on the cost, which can be used to measure the suboptimality of feasible schedules.