DocumentCode
3500036
Title
ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells
Author
Wei, Xing ; Tang, Wai-Chung ; Diao, Yi ; Wu, Yu-Liang
Author_Institution
Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Shatin, China
fYear
2012
fDate
Jan. 30 2012-Feb. 2 2012
Firstpage
511
Lastpage
516
Abstract
To maintain a lower re-masking cost, Engineering Change Order (ECO) using pre-placed spare cells for buffer insertion and gate sizing has been shown to be practical for fixing timing violating paths (ECO paths). However, in the previously known best scheme DCP [1, 2], re-routings are done with each path optimized according to its surrounding available spare cells without considering potential exchanges with neighboring active cells, and spare cell arbitration between competing ECO paths are less addressed. Besides, the extra flexibility for allowing logic restructuring was not exploited. In this work, we develop a framework harnessing the following more flexible strategies to make the usage of spare cells for ECO timing optimization more powerful: (1) a negotiation based re-routing scheme yielding a more global view in solving resource competition arbitration; (2) an extended gate sizing operation to allow exchanges of active gates with spare gates of different function types through equivalent logic re-structuring. Our experiments upon MCNC and ITC benchmarks with highly injected timing violations show that compared to DCP, our newly proposed framework can cut down the average total negative slack (TNS) by 50% and reduce the number of unsolved ECO paths by 31%.
Keywords
buffer circuits; circuit optimisation; logic design; logic gates; network routing; timing circuits; DCP scheme; ECO timing optimization; ITC benchmarks; MCNC benchmarks; buffer insertion; engineering change order; equivalent logic restructuring; extended gate sizing operation; negotiation based rerouting scheme; resource competition arbitration; spare cell arbitration; spare cells; timing violating path fixing; total negative slack; Delay; Loading; Logic gates; Optimization; Routing; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific
Conference_Location
Sydney, NSW
ISSN
2153-6961
Print_ISBN
978-1-4673-0770-3
Type
conf
DOI
10.1109/ASPDAC.2012.6165006
Filename
6165006
Link To Document