DocumentCode :
3500183
Title :
A Generic Synthesizable NoC Switch with a Scalable Testbench
Author :
Govind, Vineeth ; Raik, Jaan ; Ubar, Raimund
Author_Institution :
Dept. of Comput. Eng., Tallinn Univ. of Technol.
fYear :
2006
fDate :
2-4 Oct. 2006
Firstpage :
1
Lastpage :
4
Abstract :
In this paper, a generic parametrizable VHDL description of a deflecting NoC switch is presented. In addition, a benchmark family of 8 switches representing different possible architecture configurations has been synthesized and tested. We have created a scalable testbench providing high-fault coverage test patterns for network implementations based on this switch. We will show that the testing of switches in the network has a complexity, which grows only as a square root of the number of switches in the network
Keywords :
hardware description languages; network-on-chip; semiconductor switches; NoC switch; VHDL; network implementations; testbench; Bandwidth; Communication switching; Data communication; Network topology; Network-on-a-chip; Routing; Switches; Telecommunication network topology; Telecommunication switching; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Baltic Electronics Conference, 2006 International
Conference_Location :
Tallinn
ISSN :
1736-3705
Print_ISBN :
1-4244-0414-2
Electronic_ISBN :
1736-3705
Type :
conf
DOI :
10.1109/BEC.2006.311068
Filename :
4100289
Link To Document :
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