A RTL Asynchronous FIFO Design Using Modified Micropipeline

An asynchronous FIFO which applies four-phase handshake protocol to read or write data has been designed in register-transfer level (RTL) using VHDL. The asynchronous FIFO in this paper avoids data movement in a flow-through FIFO by applying token passing scheme in its control pipelines and multiplexer in its data register bank. Two control pipelines which base on micropipeline structure are proposed and used as the control logic for the asynchronous FIFO. An asynchronous arbiter and C-element RTL structures used in the proposed asynchronous FIFO are also presented