Title :
Optimized speaker independent speech recognition system for low cost application
Author :
Teh, C.C. ; Jong, C.C. ; Siek, L. ; Loa, K.K.
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
Abstract :
Describes an ASIC design and implementation of 15-isolated-word, speaker independent speech recognition system for low cost application. The input to the IC is a 12-bit sample with a sampling rate of 11.025 kHz. The delay between the end of a word and the response from the IC is approximately 0.24s. The IC runs at 10 MHz system clock and is targeted at 0.35 μm CMOS process. The whole chip, which includes the speech recognition system core, RAM and ROM, contains about 61000 gate counts. The core die size is 1.5mm×3mm. The current design was simulated in VHDL for hardware implementation and the functionality of the IC was identical to the MATLAB simulation. The system achieves a recognition rate of 89% for the 15 isolated words.
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; circuit simulation; hardware description languages; signal sampling; speech recognition; 0.24 s; 0.35 micron; 10 MHz; 11.025 kHz; 12 bit; ASIC design; CMOS process; MATLAB simulation; VHDL; core die size; isolated words; low cost application; recognition rate; sampling rate; speaker independent speech recognition system; Application specific integrated circuits; CMOS integrated circuits; CMOS process; Clocks; Cost function; Delay; Hardware; Read only memory; Sampling methods; Speech recognition;
Conference_Titel :
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
Print_ISBN :
0-7803-6475-9
DOI :
10.1109/MWSCAS.2000.951434
