Design techniques for functional-unit power gating in the Ultra-Low-Voltage region

In order to combat the exponentially growing leakage current in modern microprocessors, researchers have recently focused on very fine-grained functional unit power gating in which units of a microprocessor, including components of the ALU and floating point processor, are quickly shut off when not in use. This method is especially effective for Ultra-Low-Voltage (ULV) processors, where the slower clock periods makes leakage especially severe. In this paper, we investigate many of the important aspects of highly aggressive functional unit power gating in the context of ULV operation. Using an optimization framework, we demonstrate that functional unit power gating with an Ideal Policy results in an average of a 39.3% drop in total functional unit energy across a range of benchmarks. Next, we examine two very simple hardware-based power gating policies that achieve near-ideal results with very little overhead. Finally, we compare a newer style of ultra-low-voltage logic, Sense-Amplifier Pass Transistor Logic (SAPTL), to CMOS and show that it requires footers that are an eighth of the size and consumes about 100 times less energy on boot-up. With this lower overhead, total energy is reduced by 49.6%.