DocumentCode
3500496
Title
CMOS scaling for the 22nm node and beyond: Device physics and technology
Author
Kuhn, Kelin J.
Author_Institution
Logic Technol. Dev., Intel Corp., Hillsboro, OR, USA
fYear
2011
fDate
25-27 April 2011
Firstpage
1
Lastpage
2
Abstract
This paper reviews options for CMOS scaling for the 22nm node and beyond. Advanced transistor architectures such as ultra-thin body (UTB), FinFET, gate-all-around (GAA) and vertical options are discussed. Technology challenges faced by all architectures (such as variation, resistance, and capacitance) are analyzed in relation to recent research results. The impact on the CMOS scaling roadmap of system-on-chip (SOC) technologies is reviewed.
Keywords
CMOS integrated circuits; system-on-chip; transistor circuits; CMOS scaling; advanced transistor architectures; device physics; system-on-chip; CMOS integrated circuits; Capacitance; Logic gates; Materials; Strain; System-on-a-chip; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on
Conference_Location
Hsinchu
ISSN
1524-766X
Print_ISBN
978-1-4244-8493-5
Type
conf
DOI
10.1109/VTSA.2011.5872206
Filename
5872206
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