DocumentCode
3500559
Title
Testability Analysis of Digital Design Verification
Author
Hahanov, V. ; Kaminska, M. ; Fomina, E.
Author_Institution
Kharkov Nat. Univ. of Radioelectronics
fYear
2006
fDate
2-4 Oct. 2006
Firstpage
1
Lastpage
4
Abstract
A new method of testability analysis of digital design verification is presented. The method describes substantial graph-schemes that give possibility to simplify the verification task and to generate test synthesis and and/or to improve faults covering for the given inputs. The topological analysis of an oriented graph and further modification by separation of operating modes (test and functional) of a digital device is the base of the proposed technique. The main goal of the presented algorithm is improvement of testability and simplification of the verification task
Keywords
design for testability; digital circuits; digital design verification; substantial graph-schemes; testability analysis; Algorithm design and analysis; Application specific integrated circuits; Costs; Design engineering; Hardware; Production; Signal design; Software testing; System testing; Zirconium;
fLanguage
English
Publisher
ieee
Conference_Titel
Baltic Electronics Conference, 2006 International
Conference_Location
Tallinn
ISSN
1736-3705
Print_ISBN
1-4244-0414-2
Electronic_ISBN
1736-3705
Type
conf
DOI
10.1109/BEC.2006.311090
Filename
4100311
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