A 3.3 V CMOS PLL with a two-stage self-feedback ring oscillator

Author

Moon, Yeon Kug ; Yoon, Kwang Sub

Author_Institution

Dept. of Electron. Eng., Inha Univ., Inchon, South Korea

Volume

1

fYear

1999

fDate

1999

Firstpage

286

Abstract

A 3.3 V PLL (phase locked loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to-frequency linearity of VCO (Voltage controlled oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30 MHz-1 GHz with a good linearity. The DC-DC voltage up/down converter is newly, designed to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6 μm n-well CMOS process. The simulation results show a locking time of 2.6 μsec at 1 GHz, lock in range of 100 MHz-1 GHz, and a power dissipation of 112 mW

Keywords

CMOS integrated circuits; DC-DC power convertors; delays; feedback oscillators; low-power electronics; phase locked loops; voltage-controlled oscillators; 112 mW; 2.6 mus; 3.3 V; 30 MHz to 1 GHz; CMOS PLL; DC-DC voltage up/down converter; delay cell; high frequency applications; linearity; lock in range; locking time; low power applications; n-well CMOS process; power dissipation; two-stage VCO; two-stage self-feedback ring oscillator; voltage-to-frequency linearity; CMOS process; DC-DC power converters; Delay; Frequency; Linearity; Low voltage; Phase locked loops; Ring oscillators; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON 99. Proceedings of the IEEE Region 10 Conference

Conference_Location

Cheju Island

Print_ISBN

0-7803-5739-6

Type

conf

DOI

10.1109/TENCON.1999.818406

Filename

818406