Self-Testing Checker Design for arbitrary number of code words of (m,n) code

FPGA technology is used to provide self-testing checker (STC) design based on ability of each LUT to implement any Boolean function of the fixed number of variables and applying two outputs CLBs consisting of two LUTs. A universal decomposition synthesis method of STC for subset of all code words (arbitrary number L of code words) of (m,n) code is suggested. It is based on separating the proper essential subtrees from the tree representing all code words of (m,n) code. Self-testing property is proved for a set V of faults including multiple stuck-at faults at each CLB input and output poles. As a rule complexity of a self-testing checker for an arbitrary number of code words of (m, n) code is less than complexity of a self-testing checker for all code words of the same (m, n) code