Compilation and architecture support for customized vector instruction extension

Author

Cong, Jason ; Ghodrat, Mohammad Ali ; Gill, Michael ; Huang, Hui ; Liu, Bin ; Prabhakar, Raghu ; Reinman, Glenn ; Vitanza, Marco

Author_Institution

Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA

fYear

2012

fDate

Jan. 30 2012-Feb. 2 2012

Firstpage

652

Lastpage

657

Abstract

Vectorization has been commonly employed in modern processors. In this work we identify the opportunities to explore customized vector instructions and build an automatic compilation flow to efficiently identify those instructions. A composable vector unit (CVU) is proposed to support a large number of customized vector instructions with small area overhead. The results show that our approach achieves an average 1.41X speedup over the state-of-art vector ISA. We also observe a large area gain (around 11.6X) over the dedicated ASIC-based design.

Keywords

application specific integrated circuits; integrated circuit design; microprocessor chips; parallel architectures; ASIC-based design; SIMD vector processors; automatic compilation flow; composable vector unit; customized vector instruction extension; Benchmark testing; Flow graphs; Kernel; Random access memory; Registers; Support vector machines; Vectors;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific

Conference_Location

Sydney, NSW

ISSN

2153-6961

Print_ISBN

978-1-4673-0770-3

Type

conf

DOI

10.1109/ASPDAC.2012.6165037

Filename

6165037