A new design for high speed and high-density carry select adders

Author

Hashemian, Reza

Author_Institution

Dept. of Electr. Eng., Northern Illinois Univ., DeKalb, IL, USA

Volume

3

fYear

2000

fDate

2000

Firstpage

1300

Abstract

An algorithm with logarithmic carry propagation delay is developed for high-density adders. The design procedure is introduced for the construction of a 64-bit adder with maximum path delay equivalent to 8 gate delays. The algorithm is based on the carry select technique with operands partitioned into very fine slices for both quick response and low gate counts. Another property observed in this algorithm is resource (hardware) sharing which is due to regularity of the carry channel structure. The design is coded in Verilog, simulated and implemented using XC4010E Xilinx FPGA technology

Keywords

adders; carry logic; delays; field programmable gate arrays; hardware description languages; integrated circuit design; logic CAD; logic simulation; 64 bit; Verilog; XC4010E Xilinx FPGA technology; carry channel structure; carry select adders; gate counts; high-density adders; logarithmic carry propagation delay; maximum path delay; operands; resource sharing; Adders; Algorithm design and analysis; CMOS logic circuits; CMOS technology; Delay effects; Field programmable gate arrays; Hardware; Multiplexing; Partitioning algorithms; Propagation delay;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.951454

Filename

951454