Deep sub-100 nm Design Challenges

Moore´s law and the scaling theory have been the guiding principle for the semiconductor industry to accomplish its rapid progress and persistent growth. Semiconductor chips had been continuously benefited from the device scaling by simultaneously achieving higher density, higher performance and lower power consumption until they reached the 100 nm technology node. However, once the silicon technology exceeded this point, i.e. in sub-100 nm nodes, some important device parameters have started to diverge from the scaling theory, such as threshold voltages and leakage currents.