Disturb-free Independently-controlled-Gate 7T FinFET SRAM cell

We propose a novel Independently-controlled-Gate (IG) 7T FinFET SRAM cell. The cell utilizes the “stacking-like” property of split-gate super-high-V_T FinFET devices to eliminate Read disturb and Half-Select disturb, and keeper and VSS-control to mitigate Read bit-line leakage. The stability and performance of the proposed cell are compared with the conventional 6T tied-gate cell and recently reported 6T-Column-Decoupled cell using TCAD mixed-mode simulations. 3D atomistic mixed-mode Monte-Carlo simulations are performed to investigate the impact of local random variations due to Fin LER. The results indicate that the proposed cell shows better cell stability and provides sufficient margins even considering intrinsic device variations.