Fast incremental link insertion in clock networks for skew variability reduction

With the advent of sub-100nm VLSI technologies, variation effects greatly increase the unwanted skew in clock distribution networks (CDNs), thereby reducing the performance of the chip. Recent works on link based non-tree CDN propose cross-link insertion in a given clock tree to reduce skew variation. However, the current methods suffer from the drawback that they are empirical in nature, requiring the user to experiment with different parameter values. Also, the methods of ignore the interaction between the different links while selecting the links for insertion. The method of (W.D. Lam et al., 2005) attempts to overcome this drawback using a statistical link insertion methodology. However, (W.D. Lam et al., 2005) is very slow even for relatively small circuits. In this paper, we propose a fast link insertion methodology which does not require selecting empirical parameters for link insertion. Our method also incrementally considers the effect of previously inserted links before choosing the next link. SPICE based Monte Carlo simulations show that our approach obtains comparable skew reduction to that of the existing approaches while drastically reducing the time taken to obtain a good link-based non-tree CDN