• DocumentCode
    3500874
  • Title

    Clock distribution architectures: a comparative study

  • Author

    Yeh, C. ; Wilke, G. ; Chen, H. ; Reddy, S. ; Nguyen, H. ; Miyoshi, T. ; Walker, W. ; Murgai, R.

  • Author_Institution
    Apache Design Sol., Mountain View, CA
  • fYear
    2006
  • fDate
    27-29 March 2006
  • Lastpage
    91
  • Abstract
    This paper evaluates and compares different clock architectures such as mesh, tree and their hybrids, on several industrial designs. The goal of our study is to gain a quantitative understanding of engineering trade-offs between different architectures with respect to clock skew, latency, timing uncertainty, and power. This understanding will lead to guidelines for determining the best clock architecture for the design specification and constraints. To the best of our knowledge, no work has been published on evaluating and comparing these architectures on real industrial designs. Our study shows that mesh-based architectures are better than tree architectures for skew (< 1ps skew) and are more robust to variations (18% reduction in timing uncertainty as compared to tree). The power penalty associated with a mesh as compared to a tree was found to be between 10-40%. Use of multiple meshes can help reduce the power penalty
  • Keywords
    clocks; integrated circuit design; logic design; clock distribution architectures; clock skew; design constraints; design specification; mesh-based architectures; power penalty; timing uncertainty; tree architectures; Application specific integrated circuits; Clocks; Computer architecture; Jitter; Microprocessors; Network synthesis; Robustness; Signal analysis; Timing; Uncertainty;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    0-7695-2523-7
  • Type

    conf

  • DOI
    10.1109/ISQED.2006.33
  • Filename
    1613118