DocumentCode
3500882
Title
A systematic study of I/O device designs for TSV-based 3D chip stacking
Author
Kang, C.Y. ; Park, H-K ; Singh, P. ; Smith, L. ; Arkalgud, S. ; Kirsch, P.D. ; Jammy, R.
Author_Institution
SEMATECH, Austin, TX, USA
fYear
2011
fDate
25-27 April 2011
Firstpage
1
Lastpage
2
Abstract
A systematic study of I/O device designs for TSV 3D chip stacking is reported. For the primary ESD circuit using SCR, a twin well structure results in minimal transient overshoot current and voltage while its triggering voltage is higher than in Deep N-well (DNW) structures. For nMOSFET-based secondary ESD circuit components, the DNW should be applied to handle the current overshoot and the design rule should be further scaled.
Keywords
electrostatic discharge; integrated circuit design; stacking; three-dimensional integrated circuits; thyristors; ESD circuit; I/O device design; TSV 3D chip stacking; deep N-well; silicon-controlled rectifier; triggering voltage; Electrostatic discharge; Fluctuations; Heating; Substrates; Through-silicon vias; Thyristors; Transient analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on
Conference_Location
Hsinchu
ISSN
1524-766X
Print_ISBN
978-1-4244-8493-5
Type
conf
DOI
10.1109/VTSA.2011.5872225
Filename
5872225
Link To Document