DocumentCode :
3500883
Title :
Post-layout gate sizing for interconnect delay and crosstalk noise optimization
Author :
Hanchate, Narender ; Ranganathan, Nagarajan
Author_Institution :
Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL
fYear :
2006
fDate :
27-29 March 2006
Lastpage :
97
Abstract :
In this paper, we develop a new post-layout gate sizing algorithm for simultaneous optimization of interconnect delay and crosstalk noise. We have modeled the problem of gate sizing as a normal form game and solved using the Nash equilibrium. The noise induced on a net depends on the size of the gates driving the coupled nets and itself. Increasing the gate size of the driver increases the noise induced by the net on its coupled nets, where as, increasing the size of the driver of coupled nets increases the noise induced on the net itself, resulting in a conflicting situation. The problem of post-layout gate size optimization is difficult to solve due to its conflicting nature (M. R. Becer, 2003). Game theory provides a natural framework for handling such conflicting situations and allows multi-metric optimization. We have exploited this property of game theory to solve the cyclic dependency of crosstalk noise on its gate sizes, while modeling the problem of gate sizing for simultaneous optimization of interconnect delay and crosstalk noise, which again are conflicting in nature. Experimental results on several medium and large opencore designs indicate average improvements of 13.33% and 16.61% for interconnect delay and crosstalk noise, without any area overhead or need for re-routing
Keywords :
circuit optimisation; crosstalk; game theory; integrated circuit interconnections; integrated circuit layout; integrated circuit noise; Nash equilibrium; crosstalk noise optimization; game theory; gate size optimization; interconnect delay; multimetric optimization; normal form game; post-layout gate sizing; Capacitance; Circuit noise; Coupling circuits; Crosstalk; Delay effects; Game theory; Integrated circuit interconnections; Iterative algorithms; Timing; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2523-7
Type :
conf
DOI :
10.1109/ISQED.2006.101
Filename :
1613119
Link To Document :
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