DocumentCode
3500969
Title
SOS wafer Cu pillar bumping process development for flip chip package application
Author
John, Jomy ; Zhiyuan Yang
Author_Institution
Peregrine Semicond., San Diego, CA, USA
fYear
2012
fDate
13-16 Aug. 2012
Firstpage
1
Lastpage
7
Abstract
Cu pillar bumping process has been developed on SOS (Silicon on Sapphire) wafer for flip chip package application while in the initial packaging experiment open failure has been found. Voiding in bump pad metal has been found in package failure analysis. The cracks initiated from the voiding have also been captured. Further investigation has confirmed that the surface roughness of bump pad metal is closely related to this failure. The voiding was formed for that the bump pad metal was etched away by plating solvent in bumping process. Solutions on process and bump metal structure design have been discussed and presented with evaluation experiment results in this paper.
Keywords
copper; failure analysis; flip-chip devices; silicon-on-insulator; surface cracks; surface roughness; voids (solid); Cu; SOS wafer pillar bumping process development; Si; bump metal structure design; bump pad metal voiding; cracks; flip chip package; package failure analysis; plating solvent; silicon on sapphire wafer; surface roughness; Abstracts; Etching; Metallization; Solid modeling; Solvents; Tungsten;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), 2012 13th International Conference on
Conference_Location
Guilin
Print_ISBN
978-1-4673-1682-8
Electronic_ISBN
978-1-4673-1680-4
Type
conf
DOI
10.1109/ICEPT-HDP.2012.6474555
Filename
6474555
Link To Document