Title :
On test and repair of 3D random access memory
Author :
Wu, Cheng-Wen ; Lu, Shyue-Kun ; Li, Jin-Fu
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu, Taiwan
fDate :
Jan. 30 2012-Feb. 2 2012
Abstract :
The three-dimensional (3D) random access memory (RAM) using through-silicon via (TSV) has been considered as a promising approach to overcome the memory wall. However, cost and yield are two key issues for volume production of 3D RAMs, and yield enhancement increasingly requires test techniques. In this paper, we first introduce issues and existing techniques for the testing and yield enhancement of 3D RAMs. Then, a built-in self-repair (BISR) technique for 3D RAM using global redundancy is presented. According to the redundancy analysis results of each die with the BISR circuit, the die-to-die (d2d) and wafer-to-wafer (w2w) stacking problems are transferred to the bipartite maximal matching problem. Then, heuristic algorithms are also proposed to optimize the stacking yield.
Keywords :
built-in self test; integrated circuit testing; random-access storage; three-dimensional integrated circuits; 3D RAM; BISR technique; TSV; bipartite maximal matching problem; built-in self-repair technique; d2d stacking problems; die-to-die stacking problems; heuristic algorithms; three-dimensional random access memory; through-silicon via; w2w stacking problems; wafer-to-wafer stacking problems; Built-in self-test; Maintenance engineering; Random access memory; Redundancy; Registers; Stacking; Three dimensional displays;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific
Conference_Location :
Sydney, NSW
Print_ISBN :
978-1-4673-0770-3
DOI :
10.1109/ASPDAC.2012.6165054
