Transient IR voltage drops in CMOS-based power distribution networks

Author

Tang, Kevin T. ; Friedman, Eby G.

Author_Institution

Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA

Volume

3

fYear

2000

fDate

2000

Firstpage

1396

Abstract

Decreased power supply levels have reduced the tolerance to voltage changes within power distribution networks in CMOS integrated circuits. High on-chip currents, required to charge and discharge large on-chip loads while operating at high frequencies, produce significant transient IR voltage drops within a power distribution network. Analytical expressions characterizing these transient IR voltage drops are presented in this paper. The peak value of the transient IR voltage drops based on the analytical expressions is within 6% as compared to SPICE. Circuit- and layout-level design constraints to manage the peak value of the transient IR voltage drops are also discussed

Keywords

CMOS integrated circuits; VLSI; electric potential; integrated circuit design; integrated circuit modelling; power supply circuits; transient analysis; CMOS integrated circuits; CMOS-based power distribution networks; VLSI technology; analytical model; circuit-level design constraints; design constraint expressions; layout-level design constraints; peak IR voltage drops; transient IR voltage drops; CMOS integrated circuits; CMOS logic circuits; Frequency; Intelligent networks; Power distribution; Power supplies; Power systems; SPICE; Transient analysis; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.951474

Filename

951474