Flat CORDIC: a unified architecture for high-speed generation of trigonometric and hyperbolic functions

Advances in VLSI technology provided the impetus for porting algorithms into architectures. The CORDIC algorithm reigned supreme in this regard due to its canny ability to decimate trigonometric and hyperbolic functions with simple shift and add operations. Despite further refinements of the algorithm with the introduction of redundant arithmetic and higher radix CORDIC techniques, in terms of circuit latency and performance, the iterative nature remains the major bottleneck for further optimization. Although several techniques have been proposed to minimize this drawback, a technique known as flat CORDIC aims to eliminate it completely. In flat CORDIC, the conventional X and Y recurrences are successively substituted to express the final vectors in terms of the initial vectors. This results in a single equation to compute the complex trigonometric and hyperbolic functions. In this paper, the techniques devised for the VLSI efficient implementation of a 16-bit unified flat CORDIC architecture are presented. The 16-bit architecture has been synthesized using 0.35 μ CMOS process library. Finally, a detailed comparison with other major contributions show that the flat CORDIC based sine-cosine generators are, on an average, 30% faster with a significant 30% saving in silicon area