DocumentCode
3501200
Title
Analysis of a memristor based 1T1M crossbar architecture
Author
Yakopcic, Chris ; Taha, Tarek M. ; Subramanyam, Guru ; Pino, Robinson E. ; Rogers, Stanley
Author_Institution
Univ. of Dayton, Dayton, OH, USA
fYear
2011
fDate
July 31 2011-Aug. 5 2011
Firstpage
3243
Lastpage
3247
Abstract
The recently discovered memristor has the potential to be the building block of a high-density memory system. A memristor based crossbar memory system was analyzed in terms of timing and switching energy using SPICE. The memristor model in the simulations was designed to match the I-V characteristics of three different published devices. The simulation results for each device were compared to demonstrate the performance of a one transistor one memristor (1T1M) memristor crossbar.
Keywords
SPICE; electronic switching systems; memory architecture; memristors; timing circuits; transistors; 1T1M crossbar architecture; SPICE; high-density memory system; memristor based crossbar memory system; one transistor one memristor crossbar architecture; switching energy; Data models; Logic gates; Memristors; Resistance; Simulation; Switches; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks (IJCNN), The 2011 International Joint Conference on
Conference_Location
San Jose, CA
ISSN
2161-4393
Print_ISBN
978-1-4244-9635-8
Type
conf
DOI
10.1109/IJCNN.2011.6033651
Filename
6033651
Link To Document