SRAM local bit line access failure analyses

Due to the increasing process parameter variations and bitline capacitance, design of fast, reliable and robust read/write circuits for nanoscale SRAMs is a challenge. In this paper, we have investigated the effect of threshold voltage variations on the stability of read and write access schemes in SRAM designs. We considered three small signals read out and two write schemes to establish the SRAM local bitline failure trends and behavior under aggressive timing constraints and in the presence of process variations. The critical transistors in both the memory cell and the sense circuits are determined using corner analyses. Detailed simulation analyses are then performed by randomly varying the threshold voltages of these critical transistors, and the failing probabilities and points are then determined. Observations and conclusions on the failure trends of both the read and write operations are presented