Algorithm for synthesizing design context-aware fast carry-skip adders

The most timing critical part of logic design usually contains one or more arithmetic operations, in which addition is commonly involved. The carry-skip adder, which is designed to reduce the time needed to propagate the carry by skipping over groups of consecutive adder stages, is known to be comparable in speed to the carry look-ahead technique while it uses less logic area and less power. Nevertheless, only recently has it become popular, mainly because of its high synthesis complexity and complicated timing analysis, especially false path analysis. In this paper, we address the problem of automatic and systematic synthesis of (true) timing minimal carry-skip adder in the context of the whole design containing the adder. Precisely, unlike the previous works which invariably assume a uniform or a fixed pattern of input arrival times, thus limiting their application to the optimization of an isolated single addition or additions in specific design structures, e.g., final addition in a parallel multiplier, our synthesis algorithm allows to accept any arbitrary, but known in advance, bit-level arrival times of the addends and generates a structure of carry-skip adder that leads to minimize the timing of the whole design. We formulate the carry group (or block) partitioning problem for minimal timing into a dynamic programming problem and solved it effectively. The experimental results with various arithmetic designs show that our synthesis algorithm is able to reduce the circuit timing by up to 16% and 10%, compared with the results produced by the conventional optimal algorithm in [1], which does not support the variation of input times and the algorithm in [2], which nearly optimally supports only a specific pattern of input time variation. In addition, the proposed algorithm is very fast, taking only 2 seconds in synthesizing 256-bit two-level carry-skip adder.