Clock skew scheduling under process variations

Process variation may lead to chip fail because of the property variation of its datapath and clock network. We consider the problem of finding an optimal clock schedule, which has not only the minimal clock period but also the maximal tolerant to process variation. Clock skew scheduling is modeled as a constraint difference system, which can be solved by graph theory. The basic traditional algorithm has the vulnerability that the skew value is near to the skew constraint boundary. The parametric shortest path algorithm inserts unified margin value in the skew constraint with loss of circuit performance. We present an approach that can maximize the safe margin during clock skew scheduling, which is evaluated by center error square index. Experimental results show that our incremental slack distribution algorithm has the optimal clock skew scheduling result with more safe margin and has more robust tolerant to process variation