DocumentCode :
3501348
Title :
Design challenges for high performance and power efficient graphics and mobile memory interfaces
Author :
Wei, Jason ; Amirkhany, Amir ; Yuan, Chuck ; Leibowitz, Brian ; Frans, Yohan ; Nguyen, Nhat
Author_Institution :
Rambus Inc., Sunnyvale, CA, USA
fYear :
2011
fDate :
25-27 April 2011
Firstpage :
1
Lastpage :
2
Abstract :
Future generation graphics applications require more than 1TB/s memory bandwidth with a constant power budget as in today´s systems. In contrast, future mobile applications require power optimized memory interfaces that can provide sufficient memory bandwidth on the order of 25GB/s. The difference in the optimization criteria results in different design challenges and consequently, different architectural and circuit-level design tradeoffs. In this paper, we compare two different memory interface design examples, one from each area operating at 16Gbps and 3.2Gbps per pin respectively, and highlight their major differences in terms of driver and receiver design, as well as clock generation and distribution. We will also discuss some of the problems facing future generations of memory interfaces that push the limits of performance and power efficiency.
Keywords :
DRAM chips; computer graphic equipment; low-power electronics; mobile computing; power aware computing; bit rate 16 Gbit/s; bit rate 3.2 Gbit/s; byte rate 25 GByte/s; circuit-level design tradeoff; clock generation; generation graphics application; lTB memory bandwidth; mobile application; power budget; power efficient graphics; power optimized mobile memory interface; Bandwidth; Clocks; Graphics; Memory management; Mobile communication; Noise; Random access memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on
Conference_Location :
Hsinchu
ISSN :
1524-766X
Print_ISBN :
978-1-4244-8493-5
Type :
conf
DOI :
10.1109/VTSA.2011.5872247
Filename :
5872247
Link To Document :
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