DocumentCode
3501495
Title
A data-replace-controlled cache memory system and its performance evaluations
Author
Maki, N. ; Hoson, K. ; Ishida, A.
Author_Institution
Grad. Sch. of Inf. Syst., Univ. of Electro-Communs., Tokyo, Japan
Volume
1
fYear
1999
fDate
1999
Firstpage
471
Abstract
We present a novel cache memory system to reduce cache miss ratio. It enables the cache to lock or release the data in it by software controls. The paper describes its overall hardware and programming directions and also shows performance evaluations. The results show that the computer with this system can reduce the cache misses by up to 60.9% and can execute faster than a computer with a conventional cache
Keywords
cache storage; computer architecture; multiprogramming; performance evaluation; storage management; cache miss ratio; conventional cache; data-replace-controlled cache memory system; performance evaluations; programming; software control; Cache memory; Computer architecture; Control systems; Data engineering; Degradation; Hardware; Information systems; Microprocessors; Pollution; Prefetching;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON 99. Proceedings of the IEEE Region 10 Conference
Conference_Location
Cheju Island
Print_ISBN
0-7803-5739-6
Type
conf
DOI
10.1109/TENCON.1999.818453
Filename
818453
Link To Document