Improvements to CBCM (charge-based capacitance measurement) for deep submicron CMOS technology

Accurate measurement and analysis of interconnect capacitance is a critical component of nanometer technology verification. The charged-based capacitance measurement (CBCM) technique has been widely adopted as a robust technique to measure on-chip capacitance test structures. In this paper we present two design improvements for CBCM. The first is an area reduction by using bused circuit architecture to reduce probe pad area required for the test structure input and output signals. The second improvement involves techniques to reduce the impact of gate leakage and charge injection currents in 90 and 65nm process technology nodes. At the 90nm node we demonstrate accuracy improvement of an order of magnitude for small test structures