An assessment of patterning options for 15nm half-pitch

Despite the challenges in scaling below 20nm half-pitch, several technology roadmaps show applications with 15nm half-pitch patterning requirements as early as 2014~2015. These include 15nm node NAND wordlines, and possibly active/STI and bitline; as well as 15nm node fin patterning for Logic, if the FinFET technology is adopted. This timing, however, is well in advance of the EUV manufacturing tool roadmaps for 3^rd or 4^th generation EUV scanners; the current 15nm proof of concept used a laboratory configuration combining high numerical aperture (>;0.3), off-axis illumination from a synchrotron light-source, and pseudo-phase-shift-masks. Therefore, the industry will most likely need to turn to process integration schemes and apply density multiplication techniques to achieve the 15nm half-pitch from existing manufacturing technologies.